Quartus Pin Assignment File

 

 

 

Pin-Out File (.pin)

 


An ASCII text file (with the extension .pin) that contains pin assignments and other pin information for the device you specified for a design in the current Compiler settings. The Pin-Out File, which the Fitter generates, has the same name as the Compiler settings and contains the Compiler settings name; the device you specified for the design in the Compiler settings; the pin assignments for the device; and the I/O standard, voltage setting, and pin type of the pins.

 

Note:

  1. When you change the design files for a set of Compiler settings, the Fitter may change the pin assignments for the device. To retain the current pin assignments for future compilations, back-annotate the assignments.
     

  2. If you turned on Base the Pin-Out File (.pin) and Floorplan Package Views on the Largest Selected SameFrame Device in the Migration Devices dialog box, which is available from the Device dialog box, the Pin-Out File contains information for the largest SameFrame device in the Selected migration devices list in the Migration Devices dialog box, rather than for the device you specified in the current Compiler settings.

 

  1. March 1st, 2010, 02:36 AM#1
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    Pin assignment in Quartus II

    Hi all,

    After my design is added to the project if I tried to assign the pins automatically using compile Design option or I/O assignment analysis option available under compile design tool is giving a critical warning stating that "No exact pin location assignment for 29 pins of 49 total pins". This is happening for all my designs. Only Data pins are getting allocated every time i tried.

    Although i can allocate them manually using pin planner, but I need the default or suggested pin allocations.

    Kindly help me
  2. March 1st, 2010, 02:43 AM#2
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    Re: Pin assignment in Quartus II

    Forgot to mention the tool used. Quartus II

  3. Re: Pin assignment in Quartus II

    Hi,

    it is not clear to me what you try to achieve ? Do you have a board with an FPGA and want to assign your design ports to certain FPGA pins ? Can you post your <>.qsf file ?

    Kind regards

    GPK
    Originally Posted by laxmanvv
    Forgot to mention the tool used. Quartus II
  4. March 1st, 2010, 11:11 PM#4
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    Re: Pin assignment in Quartus II

    I believe if you want to let Quartus II do the pin assignments for you, you don't have to go to pin assignment. Just compile the project and finish routing. It should be able to assign the pins for you randomly.
  5. March 2nd, 2010, 12:36 AM#5
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    Re: Pin assignment in Quartus II

    No its not allocating the pins even I just compiled the design. Just beacause it is not allocating I choose pin planner. I want the allocation without pin planner involvement.

  6. Re: Pin assignment in Quartus II

    You can allocate the pins in the HDL

    in SystemVerilog do:
    module a(
    (* chip_pin = "A13" *) input wire LVDS_RX,
    (* chip_pin = "A14" *) output reg LVDS_TX);
  7. March 2nd, 2010, 04:00 PM#7
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    Re: Pin assignment in Quartus II

    Last edited by kito; March 2nd, 2010 at 04:19 PM.
    Laxmanv. I assume you want to compile your design and stop quartus from warning about assigned pin locations? Is this what your asking?

    Normally if your using a dev kit, do not let quartus do pin assigment. However if your on a new design, then just compile it and quartus fitter will assign pins. Then use back annote assignments command.
  8. March 2nd, 2010, 09:13 PM#8
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    Re: Pin assignment in Quartus II

    Yeah, what you need to do is let Quartus II handle the random pin assignments. I believe it is the same for Xilinx ISE. Then after that, go to pin output file (in txt format) to view the pin report that is assigned by Quartus II
  9. March 3rd, 2010, 09:44 PM#9
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    Re: Pin assignment in Quartus II

    But I want the allocations in QSF. Lets take an example of Xilinx MIG. If we select any banks for user allocation then the pins get allocated in the selected banks by following pin allocation rules. If we didn't select any banks it 'll proceed with Default bank selections and outputs the UCF(user copnstraints file) with all pin alloctaions. I want the similar way here.
    Is there any option like that in IPtool bench or Quartus II?.

  10. Re: Pin assignment in Quartus II

    Hi,

    looks like that my post is missing.

    you can preserve the pin assignment choosen by Quartus. You have to back-annotade the assignment. You can do that in following way:

    Choose:

    Assignment -> Back-Annotate Assignments

    Stay with the default setting "Pin&device Assignment" and press ok.

    The assignments are now written into the QSF.

    Kind regards

    GPK
    Originally Posted by laxmanvv
    But I want the allocations in QSF. Lets take an example of Xilinx MIG. If we select any banks for user allocation then the pins get allocated in the selected banks by following pin allocation rules. If we didn't select any banks it 'll proceed with Default bank selections and outputs the UCF(user copnstraints file) with all pin alloctaions. I want the similar way here.
    Is there any option like that in IPtool bench or Quartus II?.

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